1. Field of the Invention
The present invention generally relates to a voltage generating circuit which can be used in a reference voltage generating circuit, a temperature compensating circuit of a voltage comparator, a current source including a combination of a temperature sensor and a resistor having a linear temperature characteristic, and so forth. In particular, the present invention relates to a voltage generating circuit employing field effect transistors (which will be described in examples in which MOS-type field effect transistors are employed) generating a voltage proportion to the absolute temperature (PTAT: Proportional-To-Absolute-Temperature).
Further, the present invention relates to a reference voltage source circuit used in an analog circuit or the like, in particular, a reference voltage source circuit employing field effect transistors (which will be described in examples in which MOS-type field effect transistors are employed) which operates stably even at a temperature not lower than 80xc2x0 C., generates a voltage proportional to the absolute temperature (PTAT) and thus has a desired temperature characteristic.
2. Description of the Related Art
A PTAT circuit is known as a voltage generating circuit employing bipolar transistors. A PTAT circuit which achieves this art by utilizing a weak inversion range of a MOS (or CMOS) transistor has been also proposed. Further, as a reference voltage source, a reference voltage source such that a voltage source having a positive temperature coefficient is produced by causing a field effect transistor to operate in a weak inversion range, and, using it, a reference voltage source having a small variation in characteristic with respect to temperature is achieved is also known. These arts will now be described.
For example, E. Vittoz and J. Fellrath, xe2x80x9cCMOS Analog Integrated Circuits Based on Weak Inversion Operationxe2x80x9d, Vol. SC-12, No. 3, pages 224-231, June, 1997 (reference B) discloses a PTAT (Proportional-To-Absolute-Temperature) employing CMOS transistors. Thereby, a drain current ID in a weak inversion range is given by the following equation:
ID=SIDOexp(VG/nUT){exp(xe2x88x92VS/UT)xe2x88x92exp(xe2x88x92VD/UT)}
There, VG, VS and VD denote a voltage between a substrate and a gate, a voltage between the substrate and a source, and a voltage between the substrate and a drain, respectively; S denotes a ratio (Weff/Leff) of effective channel width W and channel length L; IDO denotes a characteristic current determined by process technology; n denotes a slope factor (rising characteristic in a weak inversion range); and UT denotes kT/q. There, k denotes the Boltzmann""s constant; T denotes the absolute temperature; and q denotes the charge of carrier (electron).
Further, Tsividis and Ulmer, xe2x80x9cA CMOS Voltage Referencexe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. SC-13, No. 6, pages 774-778, December, 1978 (reference A) discloses, as shown in FIG. 1 of the present application, currents I1 and I2 are caused to flow through source-connected n-type-channel transistors T1 and T2, respectively, and, as a difference between gate voltages (V1xe2x88x92V2), a VPTAT is obtained as follows (see FIG. 4 of the reference A):
VPTAT=V1xe2x88x92V2=nUTln{(S2I1)/(S1I2)}
Further, in FIG. 1, where the voltage drop between base and emitter of the bipolar transistor is referred to as Vbe, and the output is referred to as Vo,
xe2x80x83Vbe+V1=V2+Vo
Accordingly, the output Vo is obtained as follows:
Vo=Vbe+(V1xe2x88x92V2)=Vbe+VPTAT
The base-emitter voltage Vbe of the bipolar transistor at the first term has a negative temperature coefficient with respect to the absolute temperature. Further, VPTAT at the second term has a positive temperature coefficient with respect to the absolute temperature. Accordingly, the output Vo obtained from addition thereof has a flat temperature characteristic.
Further, E. Vittoz and O. Neyroud, xe2x80x9cA low-voltage CMOS bandgap referencexe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 3, pages 573-577, June, 1979 (reference C) discloses, as shown in FIG. 2 of the present application, the same current I is caused to flow through gate-connected n-type-channel MOS transistors Ta and Tb, and, as a difference in source voltages therebetween, Vo is obtained as follows (see FIG. 7 of the reference C):
Vo=VPTAT=UTln(1+Sb/Sa)
The VPTAT output in each of the above-mentioned references A and C is also proportional to UTxe2x88x92kT/q.
Further, Oguey et al., xe2x80x9cMOS Voltage Reference Based on Polysilicon Gate Work Function Differencexe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 3, June, 1980 (reference D) discloses, as shown in FIG. 3 of the present application, a transistor T1 having a p+polysilicon gate and a transistor T2 having n+polysilicon gate are used as input transistors of a differential amplifier, each of these transistors is biased into a weak inversion range, a difference between the gate voltages VR=VG1xe2x88x92VG2=xcex94VG+UTln(ID1S2/ID2S1), the bandgap of the silicon xcex94VG and VPTAT: UTln(ID1S2/ID2S1) are obtained.
Further, because
xcex94VG=xcex94VGoxe2x88x92xcex1mT
it is assumed that xcex1mT=UTln(ID1S2/ID2S1), and a voltage VR which does not depend on the temperature is obtained as follows (see FIG. 9 of the reference D):
VR=xcex94VGO=1.20(V)
Thus, in the related arts, VPTAT is achieved by utilizing a weak inversion range of a MOS transistor instead of a bipolar transistor. However, when the weak inversion range is utilized, the following problems may occur:
a) Problem that, in order to cause a gate of a MOS transistor to enter a weak inversion range, a minute-current biasing circuit for weak inversion is needed:
According to the above-mentioned reference B (see the equation (12) of the reference), a drain current should satisfy the following condition in order to keep the MOS transistor in the weak inversion range:
Ixe2x89xa6{(nxe2x88x921)/e2}SxcexcCoxUT2
There, n denotes a slope factor, S denotes the ratio (Weff/Leff) of effective channel width W and channel length L, xcexc denotes the mobility of carriers in channel, and Cox denotes the capacitance of the oxide film per unit area.
Specifically, as disclosed in U.S. Pat. No. 4,327,320, April, 1982, xe2x80x9cReference Voltage Sourcexe2x80x9d, Oguey (reference E), when n=1.7, S=1, xcexc=750 (cm2/Vs), Cox=45 (nF/cm2), and UT=26 (mV), the drain current at the room temperature should be a minute one not larger than 2 nA.
b) Problem due to Influence of Parasitic Diode:
However, when operation is made in a condition of a minute drain current not larger than 2 nA as mentioned above, it is easy to be affected by a leakage current due to a parasitic diode between the drain and substrate. For example, in the above-mentioned reference D, page 268, it is disclosed that, at a temperature not lower than 80xc2x0 C., a problematic shift due to a leakage current occurs.
c) Problem that a current biasing circuit is needed for correcting a temperature characteristic of conductivity:
As disclosed U.S. Pat. No. 4,417,263, Y. Matsuura, November, 1983 (corresponding to Japanese Patent Publication No. 4-65546, reference G), by using a difference in threshold voltage between a depletion-type transistor and an enhancement-type transistor produced to have different substrate concentrations and/or channel dopings, and making conductivity thereof to be approximately equal, a reference voltage is obtained. However, a pair of MOS transistors, produced to have different substrate concentrations and/or channel dopings, have different conductivities and/or different temperature characteristics thereof. Accordingly, as disclosed by R. A. Blauschild et al., xe2x80x9cA New NMOS Temperature-Stable Voltage Referencexe2x80x9d, Vol. SC-13, No. 6, pages 767-773, December, 1978 (reference F), a current biasing circuit for correcting the temperature characteristic of conductivity is needed.
An object of the present invention is to solve the above-mentioned problems, and to achieve a voltage generating circuit employing field effect transistors which operate stably at a high temperature not lower than 80xc2x0 C. and can also be used in a strong inversion range.
Another object of the present invention is to provide a reference voltage source circuit employing field effect transistors having a desired temperature characteristic without using a minute current biasing circuit or a current biasing circuit for correcting a temperature characteristic of conductivity.
A voltage generating circuit according to the present invention comprises a plurality of field effect transistors at least partially having gates same in conductivity type but different in impurity concentration (see FIGS. 6 through 16).
The gates may be different in impurity concentration by not less than one digit.
The plurality of field effect transistors may comprise first and second field effect transistors (M1 and M2) having gates same in conductivity type but different in impurity concentration; and
the gates of the first and second field effect transistors (M1, M2) may be connected, and the difference in source voltage between the first and second field effect transistors may be output (see FIGS. 6 and 7).
The plurality of field effect transistors may comprise first and second field effect transistors (M1 and M2) having gates same in conductivity type but different in impurity concentration; and
the sources of the first and second field effect transistors may be connected, and the difference in gate voltage between the first and second field effect transistors may be output (see FIGS. 8 through 11).
The plurality of field effect transistors may comprise first and second field effect transistors (M1 and M2) having gates same in conductivity type but different in impurity concentration; and
the voltage between the gate and source of any one (M2) of the first and second field effect transistors is made to be 0 volts, and, also, the voltage between the gate and source of the other one (M1) of the first and second field effect transistors may be output (see FIGS. 8 through 11).
Thereby, it is possible to provide voltage generating circuits employing field effect transistors having various circuit configurations which operate stably at a high temperature not lower than 80xc2x0 C. and can be used not only in weak inversion but also in strong inversion.
The second field effect transistor (M2) may be an n-type-channel field effect transistor of depletion type, having the high-concentration n-type gate and having the gate and source thereof connected;
the first field effect transistor (M1) may be an n-type-channel field effect transistor (of depletion type) having a low-concentration n-type gate and having the drain thereof connected with the source of the second field effect transistor;
a third n-type-channel field effect transistor (M3) and a resistor (R) connected in series may be further provided;
a source-follower circuit is provided for applying the gate electric potential of the first field effect transistor by connecting the gate of the first field effect transistor to the connection point between the third field effect transistor and resistor; and
the gate electric potential of the first field effect transistor may be output from that connection point (see FIG. 12A).
The second field effect transistor (M2) may be an n-type-channel field effect transistor of a depletion type, having a high-concentration n-type gate and having the gate and source thereof connected;
the first field effect transistor (M1) may be an n-type-channel field effect transistor (of depletion type) having a low-concentration n-type gate and having the drain thereof connected with the source of the second field effect transistor;
a third n-type-channel field effect transistor (M3), a first resistor (R1) and a second resistor (R2) connected in series may be further provided;
a source-follower circuit may be provided for applying the gate electric potential of the first field effect transistor by connecting the gate of the first field effect transistor to the connection point between the third field effect transistor and first resistor; and
the electric potential at the connection point between the first and second resistors may be output (see FIG. 13A).
The second field effect transistor (M2) may be an n-type-channel field effect transistor of a depletion type, having a high-concentration n-type gate and having the gate and source thereof connected;
the first field effect transistor (M1) may be an n-type-channel field effect transistor (of depletion type) having a low-concentration n-type gate and having the drain thereof connected with the source of the second field effect transistor;
a third n-type-channel field effect transistor (M3), a first resistor (R1) and a second resistor (R2) connected in series may be further provided;
a source-follower circuit may be provided for applying the gate electric potential of the first field effect transistor by connecting the gate of the first field effect transistor to the connection point between the first and second resistors; and
the electric potential at the connection point between the third field effect transistor and first resistor may be output (see FIG. 14A).
Thereby, by incorporating a resistor(s) in the voltage generating circuit, it is possible to correct VPTAT for variation in impurity concentrations.
The voltage generating circuit may further comprise a resistor trimming part by which the resistances of the first and second resistors (R1 and R2) are adjusted through laser trimming or the like after diffusion and deposition process in a manufacturing stage.
The first field effect transistor (M1) and second field effect transistor (M2) may be changed into p-type-channel field effect transistors (see FIGS. 12B, 13B and 14B).
Further, it is also possible that the above-described configuration of FIG. 12A is modified as follows: a current-mirror circuit consisting of p-type-channel MOS transistors (M6 and M7) is added in a current path of a current flowing through the resistor (R) connected between the gate and source of the MOS transistor (M1) having the low-concentration (Ng1) n-type polysilicon gate shown in FIG. 12A, and the output voltage VPTAT is obtained from the source of the p-type-channel MOS transistor (M7) (see FIG. 15).
Furthermore, it is also possible to make a configuration such as to include the source-connected MOS transistor (M1) having the low-concentration (Ng1) n-type polysilicon gate and the MOS transistor (M2) having the high-concentration (Ng2) n-type polysilicon gate connected in parallel between two power supply lines VCC and GND, the electric potentials of the drains of the MOS transistor (M1) and MOS transistor (M2) are input to a differential amplifier (A1), the output of the differential amplifier (A1) is fed back to the gate of the MOS transistor (M2) via a resistor (R2), and a resistor (R1) is provided between the power supply line VCC and the gate of the MOS transistor (M2) (see FIG. 16).
Thereby, it is possible to provide voltage generating circuits employing field effect transistors of conductivity type different from the above-mentioned configurations.
A reference voltage source circuit according to the present invention comprises:
a first voltage source comprising a plurality of field effect transistors circuit at least partly having semiconductor gates same in conductivity type but different in impurity concentration and having a positive temperature coefficient; and
a second voltage source circuit comprising a plurality of field effect transistors at least partly having semiconductor gates different in conductivity type and having a negative temperature coefficient (see FIGS. 18 through 28).
The first and second voltage source circuits may comprise a first, second and third field effect transistors (M1, M2 and M3) connected in series and at least partially having semiconductor gates different in conductivity type or impurity concentration (see FIGS. 18 and 19).
The first field effect transistor (M1) may comprise a depletion-type n-type-channel field effect transistor having a high-concentration n-type gate and having the gate and source thereof connected;
the second field effect transistor (M2) may comprise an n-type-channel field effect transistor (of depletion type) having a low-concentration n-type gate;
the third field effect transistor (M3) may comprise an enhancement-type n-type-channel field effect transistor having a p-type gate and having the gate and drain thereof connected;
a source-follower circuit is provided for applying the gate electric potential of the second field effect transistor; and
the gate voltage of the second field effect transistor is output as a reference voltage (see FIG. 18)
The first field effect transistor (M1) may comprise an enhancement-type p-type-channel field effect transistor having an n-type gate and having the gate and drain thereof connected;
the second field effect transistor (M2) may comprise a p-type-channel field effect transistor (of depletion type) having a low-concentration p-type gate;
the third field effect transistor (M3) may comprise a depletion-type p-type-channel field effect transistor having a high-concentration p-type gate and having the gate and source thereof connected;
a source-follower circuit is provided for applying the gate electric potential of the second field effect transistor; and
the gate voltage of the second field effect transistor is output as a reference voltage (see FIG. 19).
The first and second voltage source circuits may comprise first, second, third and fourth field effect transistors (M1, M2, M3 and M4) at least partially having semiconductor gates different in conductivity type or impurity concentration (see FIGS. 20 through 25).
The first field effect transistor (M1) may comprise a depletion-type n-type-channel field effect transistor having an n-type gate and having the gate and source thereof connected;
the second field effect transistor (M2) may comprise an n-type-channel field effect transistor having a p-type gate;
the first and second field effect transistors are connected in series;
a source-follower circuit is provided for applying the gate electric potential of the second field effect transistor;
the third field effect transistor (M3) may comprise an n-type-channel field effect transistor having a high-concentration n-type gate and having the gate electric potential thereof applied by the source-follower circuit;
the fourth field effect transistor (M4) may comprise an n-type-channel field effect transistor having a low-concentration n-type gate;
a differential amplifier is configured to have the third and fourth field effect transistors as input transistors thereof; and
the gate electric potential of the fourth field effect transistor is output as a reference voltage (see FIG. 20).
The first field effect transistor (M1) may comprise a p-type-channel field effect transistor having an n-type gate;
the second field effect transistor (M2) may comprise a depletion-type p-type-channel field effect transistor having a p-type gate and having the gate and source thereof connected;
the first and second field effect transistors are connected in series;
a source-follower circuit is provided for applying the gate electric potential of the second field effect transistor;
the third field effect transistor (M3) may comprise an n-type-channel field effect transistor having a high-concentration n-type gate and having the gate electric potential thereof applied by the source-follower circuit;
the fourth field effect transistor (M4) may comprise an n-type-channel field effect transistor having a low-concentration n-type gate;
a differential amplifier is configured to have the third and fourth field effect transistors as input transistors thereof; and
the gate electric potential of the fourth field effect transistor is output as a reference voltage (see FIG. 21).
The first field effect transistor (M1) may comprise a depletion-type n-type-channel field effect transistor having an n-type gate and having the gate and source thereof connected;
the second field effect transistor (M2) may comprise a n-type-channel field effect transistor having a p-type gate;
the first and second field effect transistors are connected in series;
a source-follower circuit is provided for applying the gate electric potential of the second field effect transistor;
the third field effect transistor (M3) may comprise an n-type-channel field effect transistor (of depletion type) having the high-concentration n-type gate and having the gate electric potential thereof applied by the source-follower circuit;
the fourth field effect transistor (M4) may comprise an n-type-channel field effect transistor (of depletion type) having a low-concentration n-type gate and having the gate and source thereof made to be at a ground electric potential (GND);
the third and fourth field effect transistors are connected in series; and
a reference voltage is output from the connection point between the third and fourth field effect transistors (see FIG. 22).
The first field effect transistor (M1) may comprise a p-type-channel field effect transistor having an n-type gate;
the second field effect transistor (M2) may comprise a depletion-type p-type-channel field effect transistor having a p-type gate and having the gate and source thereof connected;
the first and second field effect transistors are connected in series;
a source-follower circuit is provided for applying the gate electric potential of the first field effect transistor;
the third field effect transistor (M3) may comprise a p-type-channel field effect transistor having a low-concentration n-type gate and having the gate electric potential thereof applied by the source-follower circuit;
the fourth field effect transistor (M4) may comprise a p-type-channel field effect transistor having a high-concentration n-type gate and having the gate and drain thereof connected;
the third and fourth field effect transistors are connected in series; and
a reference voltage is output from the connection point between the third and fourth field effect transistors (see FIG. 23).
The first field effect transistor (M1) may comprise a depletion-type n-type-channel field effect transistor having an n-type gate and having the gate and source thereof connected;
the second field effect transistor (M2) may comprise an n-type-channel field effect transistor having a p-type gate;
the first and second field effect transistors are connected in series;
a source-follower circuit is provided for applying the gate electric potential of the second field effect transistor;
the third field effect transistor (M3) may comprise a depletion-type p-type-channel field effect transistor having a high-concentration p-type gate and having the gate and source thereof connected;
the fourth field effect transistor (M4) may comprise a depletion-type p-type-channel field effect transistor having a low-concentration p-type gate and having the gate electric potential thereof applied by the source-follower circuit;
the third and fourth field effect transistors are connected in series; and
a reference voltage is output from the connection point between the third and fourth field effect transistors (see FIG. 24).
The first field effect transistor (M1) may comprise a p-type-channel field effect transistor having an n-type gate;
the second field effect transistor (M2) may comprise a depletion-type p-type-channel field effect transistor having a p-type gate and having the gate and source thereof connected;
the first and second field effect transistors are connected in series;
a source-follower circuit is provided for applying the gate electric potential of the first field effect transistor;
the third field effect transistor (M3) may comprise a depletion-type n-type-channel field effect transistor having a high-concentration n-type gate and having the gate electric potential thereof applied by the source-follower circuit;
the fourth field effect transistor (M4) may comprise a depletion-type n-type-channel field effect transistor having a low-concentration n-type gate and having the gate and source thereof connected;
the third and fourth field effect transistors are connected in series; and
a reference voltage is output from the connection point between the third and fourth field effect transistors (FIG. 25).
At least any one of the first and second voltage source circuits is employed a plurality of times (see FIGS. 26 and 27).
The second voltage source circuit may comprise a first field effect transistor (M1) comprising a depletion-type n-type-channel field effect transistor having an n-type gate and having the gate and source thereof connected, and a second field effect transistor (M2) comprising an enhancement-type n-type-channel field effect transistor having a p-type gate and having the gate and drain thereof connected, the first and second field effect transistors being connected in series;
a first one of the first voltage source circuit may comprise a third field effect transistor (M3) comprising an depletion-type n-type-channel field effect transistor having a high-concentration n-type gate and having the gate electric potential thereof applied by the drain voltage of the second field effect transistor and a fourth field effect transistor (M4) comprising a depletion-type n-type-channel field effect transistor having a low-concentration n-type gate and having the gate and source thereof made to be a ground electric potential (GND), the third and fourth field effect transistors being connected in series;
a second one of the first voltage source circuit may comprise a fifth field effect transistor (M5) comprising a depletion-type n-type-channel field effect transistor having the gate electric potential thereof applied by the voltage at the connection point between the third and fourth field effect transistors and a sixth field effect transistor (M6) comprising a depletion-type n-type-channel field effect transistor having a low-concentration n-type gate and having the gate and source thereof made to be the ground electric potential (GND), the fifth and sixth field effect transistors being connected in series; and
a reference voltage is output from the connection point between the fifth and sixth field effect transistors (see FIG. 26).
The second voltage source circuit may comprise a first field effect transistor (M1) comprising a depletion-type n-type-channel field effect transistor having an n-type gate and having the gate and source thereof connected, and second and third field effect transistors (M2 and M3) each comprising an enhancement-type n-type-channel field effect transistor having a p-type gate and having the gate and drain thereof connected, the first, second and third field effect transistors being connected in series;
a first one of the first voltage source circuit may comprise a fourth field effect transistor (M4) comprising a depletion-type n-type-channel field effect transistor having a high-concentration n-type gate and a fifth field effect transistor (M5) comprising a depletion-type n-type-channel field effect transistor having a low-concentration n-type gate and having the gate and source thereof made to be a ground electric potential (GND), the fourth and fifth field effect transistors being connected in series;
a second one of the first voltage source circuit may comprise a sixth field effect transistor (M6) comprising a depletion-type n-type channel field effect transistor having a high-concentration n-type gate and having the gate electric potential thereof applied by the voltage at the connection point between the fourth and fifth field effect transistors and a seventh field effect transistor (M7) comprising a depletion-type n-type-channel field effect transistor having a low-concentration n-type gate and having the gate and source thereof made to be the ground electric potential (GND), the sixth and seventh field effect transistors being connected in series; and
a reference voltage is output from the connection point between the sixth and seventh field effect transistors (see FIG. 27).
Field effect transistors of the first and second-voltage source circuits may at least partially have gates different in conductivity type or impurity concentration, and does not employ channel doping (see FIG. 28).
The second voltage source circuit may comprise a first field effect transistor (M1) comprising an enhancement-type n-type-channel field effect transistor having an n-type gate and having the gate and source thereof connected, and a second field effect transistor (M2) comprising an enhancement-type n-type-channel field effect transistor having a p-type gate and having the gate and drain thereof connected, the first and second field effect transistors being connected in series;
a first one of the first voltage source circuit may comprise a third field effect transistor (M3) comprising an n-type-channel field effect transistor having a high-concentration n-type gate and a fourth field effect transistor (M4) comprising an enhancement-type n-type-channel field effect transistor having a low-concentration n-type gate and having the gate and source thereof made to be a ground electric potential (GND), the third and fourth field effect transistors being connected in series;
a second part of the first voltage source circuit may comprise a fifth field effect transistor (M5) comprising an n-type-channel field effect transistor having a high-concentration n-type gate and having the gate electric potential thereof applied by the voltage at the connection point between the third and fourth field effect transistors and a sixth field effect transistor (M6) comprising an enhancement-type n-type-channel field effect transistor having a low-concentration n-type gate and having the gate and source thereof made to be the ground electric potential (GND), the fifth and sixth field effect transistors being connected in series; and
a reference voltage is output from the connection point between the fifth and sixth field effect transistors (see FIG. 28).
Thereby, it is possible to achieve a voltage source circuit having a desired temperature characteristic without employing a minute current biasing circuit or a current biasing circuit for correcting temperature characteristic of conductivities. Especially, because above-mentioned various circuit configurations can be employed, it is possible to widen the range through which the present invention can be applied.
Further, the drain currents of each pair of the field effect transistors are made equal. Accordingly, as will be described, VPTAT and VPN can be obtained.
Further, each gate may comprise single-crystal silicon. Thereby, as will be described, it is possible to obtain VPTAT determined only by the impurity concentrations of the gates.
Alternatively, each gate may comprise polysilicon, and approximately 98% of the dangling bonds thereof may be terminated. Thereby, same as the case of the single-crystal silicon, it is possible to obtain VPTAT determined only by the impurity concentrations of the gates.
Alternatively, each gate may comprise polycrystal SixGe1xe2x88x92x, and composition ratio of SixGe1xe2x88x92x may be such that approximately
0.01 less than X less than 0.5
Thereby, same as the case of the single-crystal silicon, it is possible to obtain VPTAT determined only by the impurity concentrations of the gates.
Other objects and further features of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.